It is desirable in both the microelectronics and in nanotechnology industries to be able to deposit materials, which can act as fabrication aids, but which can be easily removed once fabrication is complete. One example of this in the nanotechnology area is the use of SiO2 as a fabrication aid used to help fabricate silicon cantilever structures. Once the fabrication is complete, the SiO2 can be removed by etching in aqueous HF without affecting the silicon. The use of aqueous solvents to remove the SiO2, however, can cause collapsing of the small structures due to capillary effects, which arise during drying of the water, for example in cantilever fabrication. It has also been reported that the selective etching of silicon versus SiO2 by XeF2 can be used for this fabrication by capping the silicon with a thin organic membrane through which the XeF2 can be diffused.
One example of the use of sacrificial materials in the microelectronics industry has been the use of a sacrificial organic material to introduce voids into an organosilicate glass (OSG) to make a porous OSG. The generation of these voids will effectively lower the dielectric constant of the material because the dielectric constant of air is 1.0, while the dielectric constant of the OSG material is generally >2.7. The lower limit for dielectric constant in microelectronic fabrication is achieved by incorporation of air gaps, which exhibit an effective dielectric constant of 1.0. The use of sacrificial organic layers is one promising way to realize this.
Air gaps can be formed within the semiconductor substrate in a variety of different ways. One method to form the air gap within a device is through the deposition of a poorly conformal material, which when deposited on top of a substrate with a space between raised surfaces forms air gaps or voids between those surfaces. In this connection, the air gap is formed within the spacing between a pair of interconnect lines, when the spacing is partially filled with a poorly conformal dielectric material, as shown in FIG. 1. The poorly conformal dielectric material may be deposited, for example, by chemical vapor deposition or other means. This process, however, may not be amenable to the current dual damascene process used in copper integration, for example see U.S. Pat. No. 6,057,226.
U.S. Pat. Apple. No. 2002/0149085; and U.S. Pat. Nos. 6,472,719 B1; 6,211,057 B1; 6,297,125 B1; 6,268,277 B1; 6,238,987 B1; and 6,228,763 B1, disclose methods wherein the sacrificial material is comprised of a spin-on glass or chemical vapor deposited oxide-containing material with a high HF etch rate, that is capped with a bridge layer having an opening formed therein. The spun-on material is then removed through the opening using buffered HF. See this technique in FIG. 2.
U.S. Pat. Apple. Nos. US20040099951A1; US20040094821A1; 2002/1016888 and 2002/002563; and U.S. Pat. Nos. 6,316,347; 6,329,279; and 6,498,070; 6,713,835 B1; 6,720,655 B1 disclose methods wherein the sacrificial material is an organic polymer capped by a bridge layer having one or more openings therein which is removed via a thermal anneal under an inert environment or “burning out” the polymer with an oxidizer such as molecular oxygen (O2).